Takuya Kojima

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Amano-Laboratory, Depertment of Information and Computer Science, Keio University

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Profile

English Ver. (-> Japanese Ver.)

Research Interests


Biography

Education

Work Experience

Research Experience

Qualifications


Scholarships

  1. Repayment Exemption for Graduate Students with Excellent Achievements JASSO type-1 scholarship exemption of all of loan (2019)

Grants

Awards

  1. IEICE CPSY Young Presentation Award (2018)

Publications

International Journal

  1. Takuya Kojima, and Hideharu Amano, “A Fine-Grained Multicasting of Configuration data for Coarse-Grained Reconfigurable Architectures”, IEICE Transactions on Information and Systems, Vol.E102-D,No.7,pp.1247-1256,Jul. 2019. DOI:10.1587/transinf.2018EDP7336. [Paper]

  2. Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan and Hideharu Amano, “Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable Architectures”, IEICE Transactions on Information and Systems, Vol.E101-D, No.6, pp.1532-1540, Jun 2018. DOI: 10.1587/transinf.2017EDP7308. [Paper]

International Conference

  1. Takeharu Ikezoe, Takuya Kojima, and Hideharu Amano, “A Coarse-Grained Reconfigurable Architecture with a Fault Tolerant Non-volatile Configurable Memory”, 2019 International Conference on Field-Programmable Technology (FPT),Tianjin, China, December, 2019. (Accepted)

  2. Ryohei Tomura, Takuya Kojima, and Hideharu Amano, “A Real chip evaluation of a CNN accelerator SNACC”, Synthesis And System Integration of Mixed Information technologies(SASIMI2019), Tainan, Taiwan, October, 2019. (Accepted)

  3. Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Kazusa Musha, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo and Mitaro Namiki, “A Preliminary Evaluation of Buiding Block Computing Systems”, 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2019), Singapore, October, 2019. [Paper] [Slide]

  4. Takuya Kojima, Naoki Ando, Yusuke Matsushita and Hideharu Amano, “Demonstration of Low Power Stream Processing Using a Variable Pipelined CGRA”, 29th International Conference on Field Programmable Logic and Applications (FPL), Barcelona, Spain, September, 2019. (Demo Paper) [Paper] [Poster]

  5. Takuya Kojima and Hideharu Amano, “Refinements in Data Manipulation Method for Coarse Grained Reconfigration Architectures”, 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2019), York, United Kingdom , July, 2019. [Paper] [Slide]

  6. Hideto Kayashima, Takuya Kojima, Hayate Okuhara, Tsunaaki Shidei and Hideharu Amano, “Real Chip Performance Evaluation of Inductive Coupling TCI IP”, COOLCHIPS22, Japan, April, 2019.

  7. Takuya Kojima and Hideharu Amano, “A Configuration Data Multicasting Method for Coarse-Grained Reconfigurable Architectures”, 28th International Conference on Field Programmable Logic and Applications (FPL), Dublin, Ireland, August, 2018. [Paper] [Poster]

  8. Takuya Kojima, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Nguyen Anh Vu Doan and Hideharu Amano, “Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping”, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2018), Canada, June, 2018. [Paper] [Slide]

  9. Takeharu Ikezoe, Takuya Kojima, Hideharu Amano, Junya Akaike, Kimiyoshi Usami, Keizo Hiraga, Yusuke Shuto and Kojiro Yagami, “A micro-controller for MTJ-based Non-volatile Flip-flops for data verification”, COOLCHIPS21, Japan, April, 2018.

  10. Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Yusuke Matsushita, Naoki Ando, Mitaro Namiki and Hideharu Amano, “A shared memory chip for twin-tower of chips”, Synthesis And System Integration of Mixed Information technologies(SASIMI2018), KUNIBIKI MESSE, March 2018.

  11. Takuya Kojima, Naoki Ando, Hayate Okuhara, Hideharu Amano, “Glitch-aware Variable Pipeline Optimization for CGRAs”, ReConFig 2017, Mexico, December 2017. [Paper] [Poster]

  12. Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima and Hideharu Amano, “Scalable Deep Neural Network Accelerator Cores with Cubic Integration using Through Chip Interface”, 2017 International SoC Design Conference (ISOCC 2017), Seoul, Korea, November, 2017.

  13. Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura , Tetsui Ohkubo, Takuya Kojima and Hideharu Amano, “The Design and Implementation of Scalable Deep Neural Network Accelerator Cores”, MCSoC-17, Korea, September 2017.

  14. Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano, ““Body Bias Optimization for Variable Pipelined CGRA”, 27th International Conference on Field-Programmable Logic and Applications(FPL), Belgium, September 2017. [Paper] [Poster]

  15. Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano, “Power Optimization for CGRA with Control of Variable Pipeline and Body Bias Voltage”, COOLCHIPS20, Japan, April 2017.

Japanese domestic conferences/Technical reports

  1. 池添赳治, 小島拓也, 天野英晴 “不揮発性構成メモリを用いた耐故障性粗粒度再構成可能アーキテクチャ”, RECONF研究会, 北九州国際会議場, 福岡, 2019年9月.

  2. 小島拓也, 天野英晴, “粗粒度再構成可能アーキテクチャCMAにおけるメモリバンクアクセスの改良”, SWoPP2019, 北見市民会館, 北海道, 2019年7月. [Paper]

  3. 天野英晴, 茅島秀人, 小島拓也, 坂本龍一, 近藤正章, 並木美太郎, “ビルディングブロック型積層システムの性能評価”, SWoPP2019, 北見市民会館, 北海道, 2019年7月.

  4. 小島拓也, 天野英晴, “3次元積層型CGRAのためのアプリケーション割り当て手法の検討”, 学生・若手研究会, ホテルアトールエメラルド宮古島, 沖縄, 2018年12月.

  5. 寺嶋爽花, 小島拓也, 武者千嵯, 奥原颯, 天野英晴, “ツインタワー型共有メモリチップを用いたCNNアプリケーションの高速化”, 学生・若手研究会, ホテルアトールエメラルド宮古島, 沖縄, 2018年12月.

  6. Hideto Kayashima , Takuya Kojima, Hayate Okuhara, Hideharu Amano, “Real Chip Implementation of a verification scheme for an Inductive-Coupling ThruChip Interface”, Design Gaia 2018 -New Field of VLSI Design- , Satellite Campus Hiroshima, Hiroshima-shi, Dec. 2018.

  7. Takuya Kojima, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Ng. Doan Anh Vu, Hideharu Amano, “Low Power Stream Processing on a Variable Pipelined Accelerator CCSOTB2”, Hida Area Local Industry Promotion Center, Takayama-shi, Nov. 2018. [Paper] (Young Presentation Award)

  8. 小島拓也,安藤尚樹, 松下悠亮, 奥原 颯, Nguyen Anh Vu Doan, 天野英晴, “多目的遺伝的アルゴリズムを用いたCGRAマッピング最適化手法と実チップ評価”, RECONF研究会, LINE Fukuokaカフェスペース, 福岡, 2018年9月. [Paper]

  9. 小島拓也,安藤尚輝,天野英晴, “可変構造パイプラインを持つ粗粒度再構成アクセラレータCCSOTB2”, 第80回情報処理学会全国大会, 早稲田大学, 東京, 2018年3月. [Paper]

  10. 寺嶋爽花,小島拓也,奥原 颯,松下悠亮,安藤尚輝,並木美太郎,天野英晴, “ツインタワーのためのメモリチップ”, 第80回情報処理学会全国大会, 早稲田大学, 東京, 2018年3月.

  11. 松下悠亮,小島拓也,門本淳一郎,黒田忠広,天野英晴, マルチコア積層システムCube-2の実装と評価, 第80回情報処理学会全国大会, 早稲田大学, 東京, 2018年3月.

  12. 坂本龍一,高田 遼,石井 潤,近藤正章,中村 宏,大久保徹以,小島拓也,天野英晴 “TCIを用いた3次元積層型DNN向けアクセラレータSNACCの設計と評価”, 第80回情報処理学会全国大会, 早稲田大学, 東京, 2018年3月.

  13. 小島拓也,安藤尚輝,奥原 颯,天野 英晴,”グリッチを考慮したCGRAの可変パイプライン最適化”, デザインガイア2017 -VLSI設計の新しい大地-, くまもと県民交流館パレア, 熊本, 2017年11月. [Paper] [Poster]

  14. 安藤尚輝,小島拓也,天野英晴,”可変パイプラインCGRAの実チップ評価”, デザインガイア2017 -VLSI設計の新しい大地-, くまもと県民交流館パレア, 熊本, 2017年11月.

  15. 寺嶋爽花,小島拓也,奥原 颯,松下悠亮,安藤尚輝,並木美太郎,天野英晴,”ツインタワー用共有メモリチップの開発”, デザインガイア2017 -VLSI設計の新しい大地-, くまもと県民交流館パレア, 熊本, 2017年11月.

  16. 小島拓也, 安藤尚輝, 奥原颯, Anh Vu Doan, 天野英晴, “整数計画問題を用いたパイプライン型CGRAのボディバイアス電圧最適化”, HotSPA2017, 登別温泉第一滝本館, 北海道, 2017年5月. [Paper]

  17. 高田遼,石井潤,坂本龍一,近藤正章,中村宏,大久保徹以,小島拓也,天野英晴, “ディープニューラルネットワーク向けアクセラレータチップの設計と性能評価”, cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming(xSIG), 虎ノ門ヒルズフォーラム, 東京, 2017年4月.

  18. 小島拓也, 安藤尚輝, 松下悠亮, 奥原颯, 天野英晴, “パイプライン段数とボディバイアス電圧制御によるパイプライン型CGRAの電力削減手法の検討”, 具志川農村環境改善センター, 沖縄, 2017年3月. [Paper]

  19. 大久保徹以, 小島拓也, 天野英晴, 高田遼, 石井潤, 坂本龍一, 近藤正章, 中村宏, “無線3次元積層チップを用いたDeep Learningアクセラレータのコンパイラツールチェーン”, 具志川農村環境改善センター, 沖縄, 2017年3月.

Acknowledgement

A part of our work is supported by a Grant-in-Aid for Scientific Research(S) Grant Number 25220002, a Grant-in-Aid for Scientific Research(B) Grant Number 18H03215 and a Grant-in-Aid for JSPS Fellows Grant Number 19J21493. Also, A part of our work is supported by VLSI Design and Education Center(VDEC), the University of Tokyo in collaboration with Synopsys, Inc. and Cadence Design Systems, Inc.